Design Verification Engineer

  • Contract
  • Anywhere
Regarding experience, we are looking for 2 types of profiles:

  • Intermediate with closer/compatible profile (5-10+ years, relying on specific expertise to ramp up quickly)
  • Senior capable DV Eng with typical DV profile (10-15+ years, relying on global experience to ramp up quickly)

Please send your resume to 

Core technologies :

  • PHY and SerDes

Protocols (physical layer):

  • PIPE interface
  • PCIe
  • Ethernet
  • SRIO

Design specifics:

  • Mixed-signal design
  • Multiple clock domains
  • Low power domains
  • Equalization and adaptation algorithms
  • Interfaces to controllers (eg PIPE)

Verification techniques :

  • Metric-Driven-Verification

vPlanner, vManager, IMC, VSIFs, FC and CC analysis and closure etc.
Languages :

  • Specman-UVM
  • SV-UVM
  • SVA


  • FW implementation and verification (simulation, emulation (Palladium, protium), etc.)
  • Digital mixed-signal verification (real models, analog netlist extraction, ….)
  • Formal connectivity (Jasper)
  • Formal Property Verification (Jasper) (heavy usage of Formal Properties Verification in our flow)
  • Block to top integration
  • Lab support (scripts generation, debug, …)
  • GLS (gate level simulation)

To apply for this job please visit